1. Field of the Invention
The present invention generally relates to semiconductor devices and more particularly to field effect transistors (FETs).
2. Background Description
High performance (fast) Static Random Access Memories (SRAMs) are crucial in achieving high performance in state of the art computer systems. High Performance arrays may be integrated into a microprocessor as on-chip memory, sometimes called a level 1 (L1) cache. The microprocessor may access Data and execute instructions in the L1 cache very quickly, avoiding data transfer delays that normally occur in off-chip information transfers.
In addition to the L1 cache, a stand-alone high performance SRAM, sometimes called a level 2 (L2) cache may be strategically located between the microprocessor and a relatively slow main memory to further boost system performance. Typically, L2 cache performance matches or nearly matches microprocessor speed. By keeping larger subroutines with currently executing instructions and data in the L2 cache, so that all memory appears to the microprocessor to be as fast as the L2 cache, the microprocessor may run at or near its top speed, maximizing system performance.
State of the art SRAMs are made in the complimentary insulated gate Field Effect Transistor (FET) technology, commonly referred to as CMOS, to minimize power dissipation. Each cell includes a pair cross coupled invertors coupled to a bit line by one or more pass gates. Each inverter includes one P-type FET (PFET) and one N-type FET (NFET). Typically, the pass gates are NFETs. CMOS SRAM storage cell designs are optimized for density or performance.
The densest state of the art SRAMs cells, presently, are stacked complementary pairs of FETs sharing a common gate sandwiched between them. Normally, the PFET is stacked above the NFET. Each such stacked pair forms a CMOS inverter. Two such stacked pairs are cross coupled as the cell latch. These cross coupled stacked transistor invertors form a very dense CMOS cell.
However, the density realized from stacking the FETs may be offset by the resulting relatively poor electrical device characteristics of stacked devices (especially for the PFET) as compared to normal bulk FETs, which are typically twice as fast. Bulk FETs provide better performance than stacked device cells, but are larger, because of less efficient wiring. These high performance bulk cells typically require three interconnection levels including a special cell wiring layer and 2 normal chip metal level.
As might be expected, latch stability is crucial to the integrity of data stored therein. Prior art SRAM latches were relatively large and relatively slow compared to state of the art SRAM latches. The energy needed to switch a prior art SRAM latch from one state to another was large, so cell stability was not an issue.
However, the latches in state of the art SRAM cells are sensitive to cosmic rays and alpha particles. To counteract this sensitivity, stabilizing capacitance is added to the storage nodes in state of the art SRAM cell latches. This added capacitance has little impact on cell write time and no impact on cell read time. So, state of the art CMOS SRAM storage cell designs include this capacitance to add stability while attempting to avoid any significant impact on cell size.
It is therefore a purpose of the present invention to reduce latch size.
It is another purpose of the present invention to improve SRAM speed, density and power.
It is yet another purpose of the present invention to improve/reduce CMOS latch size.
It is yet another purpose of the present invention to improve SRAM cell stability and cell density.
The present invention is a directly coupled pair of Field Effect transistors (FETs), a latch including at least one pair of directly coupled FETs, a Static Random Access Memory (SRAM) cell including at least one pair of directly coupled FETs in a latch and the process of forming the directly coupled FET structure, latch and SRAM cell.
The FETs are, preferably, a pair of vertical epitaxial stacks separated by a gate oxide with channel regions formed such that each device""s source or drain is the gate of the other device. The preferred embodiment latch includes two such pairs of directly coupled FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. In one embodiment, the SRAM Cell includes one pass gate. In another embodiment, the SRAM cell includes two pass gates.
As preferred embodiment SRAM cells include preferred embodiment latches and preferred embodiment latches include preferred embodiment directly coupled FET pairs the preferred embodiment process of forming SRAM cells includes the process of forming the preferred latch and the preferred directly coupled FET pairs. There are three major steps in the preferred embodiment SRAM process. First, preferred embodiment latches are formed in an insulator layer on a semiconductor wafer, preferably SiO2 on silicon. Second, the cell pass gates are formed on a pass gate layer, referred to herein as an Input/Output (I/O) layer. Third, the I/O layer is bonded to and connected to the latch layer.